40 search results - page 4 / 8 » Early Power Estimation for System-on-Chip Designs |
DAC
1999
ACM
13 years 11 months ago
1999
ACM
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
TVLSI
2010
13 years 2 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techni...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
ISPD
2004
ACM
14 years 27 days ago
2004
ACM
High performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance ...