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ICCAD
2008
IEEE
141views Hardware» more  ICCAD 2008»
14 years 5 months ago
Layout decomposition for double patterning lithography
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures)...
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Ya...
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
14 years 5 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou
TLCA
2009
Springer
14 years 3 months ago
Initial Algebra Semantics for Cyclic Sharing Structures
Terms are a concise representation of tree structures. Since they can be naturally defined by an inductive type, they offer data structures in functional programming and mechanis...
Makoto Hamana
DATE
2007
IEEE
123views Hardware» more  DATE 2007»
14 years 2 months ago
Clock domain crossing fault model and coverage metric for validation of SoC design
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
Yi Feng 0002, Zheng Zhou, Dong Tong, Xu Cheng
HPCC
2007
Springer
14 years 2 months ago
On Pancyclicity Properties of OTIS Networks
The OTIS-Network (also referred to as two-level swapped network) is composed of n clones of an n-node original network constituting its clusters. It has received much attention due...
Mohammad R. Hoseinyfarahabady, Hamid Sarbazi-Azad