832 search results - page 134 / 167 » Effect of Malicious Synchronization |
ISCA
2008
IEEE
14 years 4 months ago
2008
IEEE
Modern processors rely on memory dependence prediction to execute load instructions as early as possible, speculating that they are not dependent on an earlier, unissued store. To...
IWNAS
2008
IEEE
14 years 4 months ago
2008
IEEE
We study parallel job scheduling, where each job may be scheduled on any number of available processors in a given parallel system. We propose a mathematical model to estimate a j...
MICRO
2008
IEEE
14 years 4 months ago
2008
IEEE
Uniprocessor simulators track resource utilization cycle by cycle to estimate performance. Multiprocessor simulators, however, must account for synchronization events that increas...
DATE
2007
IEEE
14 years 4 months ago
2007
IEEE
Network-on-Chip (NoC) is generally regarded as the most promising solution for the future on-chip communication scheme in gigascale integrated circuits. As traditional debug archi...
DSN
2007
IEEE
14 years 4 months ago
2007
IEEE
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...