Sciweavers

4924 search results - page 921 / 985
» Efficiency Improvement for NTRU
Sort
View
ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
14 years 6 months ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
ICCAD
2006
IEEE
103views Hardware» more  ICCAD 2006»
14 years 6 months ago
A statistical framework for post-silicon tuning through body bias clustering
Adaptive body biasing (ABB) is a powerful technique that allows post-silicon tuning of individual manufactured dies such that each die optimally meets the delay and power constrai...
Sarvesh H. Kulkarni, Dennis Sylvester, David Blaau...
ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 6 months ago
Hardware synthesis from guarded atomic actions with performance specifications
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...
Daniel L. Rosenband
ICCAD
2001
IEEE
192views Hardware» more  ICCAD 2001»
14 years 6 months ago
BOOM - A Heuristic Boolean Minimizer
We present a two-level Boolean minimization tool (BOOM) based on a new implicant generation paradigm. In contrast to all previous minimization methods, where the implicants are ge...
Jan Hlavicka, Petr Fiser
CVPR
2010
IEEE
14 years 5 months ago
Linked Edges as Stable Region Boundaries
Many of the recently popular shape based category recognition methods require stable, connected and labeled edges as input. This paper introduces a novel method to find the most st...
Michael Donoser, Hayko Riemenschneider and Horst B...