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» Efficient Design Error Correction of Digital Circuits
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DAC
1996
ACM
14 years 25 days ago
Improving the Efficiency of Power Simulators by Input Vector Compaction
Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern dependent. To obtain an accurate power estimate, a large input...
Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, ...
MJ
2007
119views more  MJ 2007»
13 years 8 months ago
Automated energy calculation and estimation for delay-insensitive digital circuits
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, ...
VTS
2003
IEEE
87views Hardware» more  VTS 2003»
14 years 1 months ago
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits
We present a novel analog checker that adjusts dynamically the error threshold to the magnitude of its input signals. We demonstrate that this property is crucial for accurate con...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
GLOBECOM
2008
IEEE
14 years 3 months ago
Joint Channel and Mismatch Correction for OFDM Reception with Time-interleaved ADCs: Towards Mostly Digital MultiGigabit Transce
— Time-interleaved (TI) analog-to-digital converters (ADCs) are a promising architecture for realizing the highspeed ADCs required to implement “mostly digital” receivers for...
P. Sandeep, Upamanyu Madhow, Munkyo Seo, Mark J. W...
ISQED
2010
IEEE
156views Hardware» more  ISQED 2010»
13 years 10 months ago
On the design of different concurrent EDC schemes for S-Box and GF(p)
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir,...