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» Efficient Design Error Correction of Digital Circuits
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ISCAS
1994
IEEE
117views Hardware» more  ISCAS 1994»
14 years 26 days ago
Design of a Fast Sequential Decoding Algorithm Based on Dynamic Searching Strategy
This paper presents a new sequential decoding algorithm based on dynamic searching strategy to improve decoding efficiency. The searching strategy is to exploit both sorting and p...
Wen-Wei Yang, Li-Fu Jeng, Chen-Yi Lee
ISPD
1999
ACM
89views Hardware» more  ISPD 1999»
14 years 1 months ago
VIA design rule consideration in multi-layer maze routing algorithms
—Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules In this pap...
Jason Cong, Jie Fang, Kei-Yong Khoo
ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
13 years 6 months ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
FPL
1999
Springer
103views Hardware» more  FPL 1999»
14 years 1 months ago
IP Validation for FPGAs Using Hardware Object Technology
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
Steve Casselman, John Schewel, Christophe Beaumont
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
14 years 5 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh