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CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures
Abstract-- We address performance maximization of independent task sets under energy constraint on chip multi-processor (CMP) architectures that support multiple voltage/frequency ...
Sushu Zhang, Karam S. Chatha
FPL
2009
Springer
161views Hardware» more  FPL 2009»
14 years 5 days ago
A multi-FPGA architecture for stochastic Restricted Boltzmann Machines
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
Daniel L. Ly, Paul Chow
SBCCI
2004
ACM
111views VLSI» more  SBCCI 2004»
14 years 1 months ago
A partial reconfigurable architecture for controllers based on Petri nets
Digital Control System in the industry has been used in most of the applications based on expensive Programmable Logical Controllers (PLC). These Systems are, in general, highly c...
Paulo Sérgio B. do Nascimento, Paulo Romero...
ASAP
2008
IEEE
145views Hardware» more  ASAP 2008»
14 years 2 months ago
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system
This article discusses the design of an application specific MPSoC architecture dedicated to Multiple Target Tracking (MTT). This application has its utility in driver assistant s...
Jehangir Khan, Smaïl Niar, Atika Rivenq, Yass...