2620 search results - page 111 / 524 » Efficient Hardware Voxelization |
127
click to vote
CGO
2004
IEEE
15 years 8 months ago
2004
IEEE
We study several major characteristics of dynamic optimization within the PARROT power-aware, trace-cachebased microarchitectural framework. We investigate the benefit of providin...
126
click to vote
ASPLOS
2008
ACM
15 years 6 months ago
2008
ACM
Increasing demand for power-efficient, high-performance computing requires tuning applications and/or the underlying hardware to improve the mapping between workload heterogeneity...
149
click to vote
DSD
2010
IEEE
15 years 2 months ago
2010
IEEE
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
155
click to vote
ATS
2010
IEEE
14 years 11 months ago
2010
IEEE
In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at...
111
click to vote
IPPS
2002
IEEE
15 years 9 months ago
2002
IEEE
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...