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DATE
2006
IEEE
128views Hardware» more  DATE 2006»
15 years 10 months ago
Efficient link capacity and QoS design for network-on-chip
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under Quality-...
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israe...
DATE
2005
IEEE
97views Hardware» more  DATE 2005»
15 years 10 months ago
Efficient Solution of Language Equations Using Partitioned Representations
A class of discrete event synthesis problems can be reduced to solving language equations F • X ⊆ S, where F is the fixed component and S the specification. Sequential synthes...
Alan Mishchenko, Robert K. Brayton, Jie-Hong Rolan...
138
Voted
ITC
2003
IEEE
153views Hardware» more  ITC 2003»
15 years 9 months ago
An Efficient and Effective Methodology on the Multiple Fault Diagnosis
In this paper, we analyze failing circuits and propose a multiple-fault diagnosis approach. Our methodology has been validated experimentally and has proved to be highly efficient...
Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadow...
ATS
2002
IEEE
108views Hardware» more  ATS 2002»
15 years 9 months ago
Fault Set Partition for Efficient Width Compression
In this paper, we present a technique for reducing the test length of counter-based pseudo-exhaustive built-in self-testing (BIST) based on width compression method. More formally...
Emil Gizdarski, Hideo Fujiwara
DATE
2000
IEEE
71views Hardware» more  DATE 2000»
15 years 9 months ago
Clocktree RLC Extraction with Efficient Inductance Modeling
In this paper, we present an efficient yet accurate inductance extraction methodology and also apply it to clocktree RLC extraction. We first show that without loss of accuracy, t...
Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie...