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ICCD
2003
IEEE
147views Hardware» more  ICCD 2003»
16 years 1 months ago
An Efficient VLIW DSP Architecture for Baseband Processing
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-...
ICCD
2002
IEEE
110views Hardware» more  ICCD 2002»
16 years 1 months ago
Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques
Practical approaches for on-chip inductance extraction to obtain a sparse, stable and accurate inverse inductance matrix K are proposed. The novelty of our work is in using circui...
Haitian Hu, Sachin S. Sapatnekar
ICCD
2000
IEEE
103views Hardware» more  ICCD 2000»
16 years 1 months ago
Efficient Place and Route for Pipeline Reconfigurable Architectures
In this paper, we present a fast and eficient compilation methodology for pipeline reconfigurable architectures. Our compiler back-end is much faster than conventional CAD tools, ...
Srihari Cadambi, Seth Copen Goldstein
132
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ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
16 years 1 months ago
Performance Efficiency of Context-Flow System-on-Chip Platform
Recent efforts in adapting computer networks into system-on-chip (SOC), or network-on-chip, present a setback to the traditional computer systems for the lack of effective program...
Rami Beidas, Jianwen Zhu
ISQED
2009
IEEE
111views Hardware» more  ISQED 2009»
15 years 11 months ago
Efficient statistical analysis of read timing failures in SRAM circuits
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pilegg...