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ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
15 years 2 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
15 years 2 months ago
Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels
Wide Single Instruction, Multiple Thread (SIMT) architectures often require a static allocation of thread groups that are executed in lockstep throughout the entire application ker...
Michael Steffen, Joseph Zambreno
ICCAD
2002
IEEE
175views Hardware» more  ICCAD 2002»
16 years 1 months ago
Efficient model order reduction via multi-node moment matching
- The new concept of Multi-node Moment Matching (MMM) is introduced in this paper. The MMM technique simultaneously matches the moments at several nodes of a circuit using explicit...
Yehea I. Ismail
ISCAS
2008
IEEE
141views Hardware» more  ISCAS 2008»
15 years 11 months ago
AMBA AHB bus potocol checker with efficient debugging mechanism
—Bus-based system-on-chip (SoC) design becomes the major integration methods for shorting design cycle and time-tomarket, thus how to verify IP functionality on bus protocol is a...
Yi-Ting Lin, Chien-Chou Wang, Ing-Jer Huang
ICCAD
2000
IEEE
94views Hardware» more  ICCAD 2000»
15 years 9 months ago
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan
––In this paper, a corner block list — a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block...
Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu,...