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CODES
2003
IEEE
15 years 10 months ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
ISCA
2002
IEEE
103views Hardware» more  ISCA 2002»
15 years 9 months ago
Efficient Dynamic Scheduling Through Tag Elimination
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
Dan Ernst, Todd M. Austin
MICRO
2000
IEEE
68views Hardware» more  MICRO 2000»
15 years 9 months ago
Efficient checker processor design
The design and implementation of a modern microprocessor creates many reliability challenges. Designers must verify the correctness of large complex systems and construct implemen...
Saugata Chatterjee, Christopher T. Weaver, Todd M....
DATE
2010
IEEE
148views Hardware» more  DATE 2010»
15 years 9 months ago
Scoped identifiers for efficient bit aligned logging
Abstract--Detailed diagnostic data is a prerequisite for debugging problems and understanding runtime performance in distributed wireless embedded systems. Severe bandwidth limitat...
Roy Shea, Mani B. Srivastava, Young Cho
ICCD
1999
IEEE
93views Hardware» more  ICCD 1999»
15 years 9 months ago
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
If a system-on-a-chip (SOC) contains an embedded processor, this paper presents a novel approach for using the processor to aid in testing the other components of the SOC. The bas...
Abhijit Jas, Nur A. Touba