515 search results - page 25 / 103 » Efficient Logic Optimization Using Regularity Extraction |
112
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DAC
2005
ACM
15 years 4 months ago
2005
ACM
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
150
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EC
2006
15 years 2 months ago
2006
Learning Classifier Systems (LCSs), such as the accuracy-based XCS, evolve distributed problem solutions represented by a population of rules. During evolution, features are speci...
109
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DATE
2003
IEEE
15 years 7 months ago
2003
IEEE
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
131
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ICCAD
2007
IEEE
15 years 11 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
123
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DAC
2001
ACM
16 years 3 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...