279 search results - page 23 / 56 » Efficient Power Co-Estimation Techniques for System-on-Chip ... |
DAC
2009
ACM
14 years 9 months ago
2009
ACM
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
With the increasing levels of variability and randomness in the characteristics and behavior of manufactured nanoscale structures and devices, achieving performance optimization u...
AHS
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, we present a low power implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implem...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
Polar modulation techniques offer the capability of multimode wireless system and the potential for the high efficiency Power Amplifier (PA). This paper describes a new design of D...