279 search results - page 28 / 56 » Efficient Power Co-Estimation Techniques for System-on-Chip ... |
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
FPL
2007
Springer
14 years 2 months ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
ICCD
2007
IEEE
14 years 5 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
RTSS
2007
IEEE
14 years 2 months ago
2007
IEEE
Wireless sensor network (WSN) applications have been studied extensively in recent years. Such applications involve resource-limited embedded sensor nodes that have small size and...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we devel...