279 search results - page 29 / 56 » Efficient Power Co-Estimation Techniques for System-on-Chip ... |
PATMOS
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
NOCS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
ICS
2009
Tsinghua U.
14 years 1 months ago
2009
Tsinghua U.
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
IEEEPACT
2002
IEEE
14 years 1 months ago
2002
IEEE
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...