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IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
14 years 28 days ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
CODES
2005
IEEE
14 years 29 days ago
A power estimation methodology for systemC transaction level models
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan
CODES
2007
IEEE
14 years 1 months ago
Probabilistic performance risk analysis at system-level
We present a novel hybrid approach for performance analysis of a system design. Unlike other approaches in this area, in this paper we do not focus on the determination of pessimi...
Alexander Viehl, Markus Schwarz, Oliver Bringmann,...
CODES
2007
IEEE
14 years 1 months ago
Combined approach to system level performance analysis of embedded systems
Compositional approaches to system-level performance analysis have shown great flexibility and scalability in the design of heterogeneous systems. These approaches often assume c...
Simon Künzli, Arne Hamann, Rolf Ernst, Lothar...
ICIP
2007
IEEE
14 years 1 months ago
Software Pipelines Design for Variable Block-Size Motion Estimation with Large Search Range
This paper presents some techniques for efficient motion estimation (ME) implementation on fixed-point digital signal processor (DSP) for high resolution video coding. First, chal...
Zhigang Yang, Wen Gao, Yan Liu, Debin Zhao