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CODES
2005
IEEE
14 years 29 days ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
CASES
2008
ACM
13 years 9 months ago
Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware
Automatic vectorization of programs for partitioned-ALU SIMD (Single Instruction Multiple Data) processors has been difficult because of not only data dependency issues but also n...
Hoseok Chang, Wonyong Sung
CODES
2006
IEEE
14 years 1 months ago
A bus architecture for crosstalk elimination in high performance processor design
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increas...
Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
CODES
2006
IEEE
14 years 1 months ago
Thermal-aware high-level synthesis based on network flow method
Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reli...
Pilok Lim, Taewhan Kim
ASAP
2000
IEEE
141views Hardware» more  ASAP 2000»
13 years 11 months ago
Bit Permutation Instructions for Accelerating Software Cryptography
Permutation is widely used in cryptographic algorithms. However, it is not well-supported in existing instruction sets. In this paper, two instructions, PPERM3R and GRP, are propo...
Zhijie Shi, Ruby B. Lee