11 Due to the increasing test data volume needed to test corebased System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In co...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Ki...
In many applications surfaces containing a large number of primitives occur. Geometry compression reduces storage space and transmission time for such models. A special case is gi...
1 This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The techni...