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ATS
2005
IEEE
91views Hardware» more  ATS 2005»
14 years 1 months ago
SOC Test Scheduling with Test Set Sharing and Broadcasting
11 Due to the increasing test data volume needed to test corebased System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In co...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 11 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
ITC
2003
IEEE
205views Hardware» more  ITC 2003»
14 years 22 days ago
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Ki...
VMV
2001
129views Visualization» more  VMV 2001»
13 years 8 months ago
Compression of Isosurfaces
In many applications surfaces containing a large number of primitives occur. Geometry compression reduces storage space and transmission time for such models. A special case is gi...
Dietmar Saupe, Jens-Peer Kuska
ITC
2002
IEEE
83views Hardware» more  ITC 2002»
14 years 11 days ago
Packet-Based Input Test Data Compression Techniques
1 This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The techni...
Erik H. Volkerink, Ajay Khoche, Subhasish Mitra