120 search results - page 12 / 24 » Efficient hardware code generation for FPGAs |
FPL
2008
Springer
13 years 9 months ago
2008
Springer
The phase detector is a main building block in phaselocked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solu...
ISSS
1999
IEEE
13 years 12 months ago
1999
IEEE
Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity o...
ICDE
2010
IEEE
14 years 7 months ago
2010
IEEE
We present the application of customized code generation to database query evaluation. The idea is to use a collection of highly efficient code templates and dynamically instantiat...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
Emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multiprocessor architectures. The advances in the FPGA chip technology make the implementation of such a...
ISSS
2000
IEEE
13 years 12 months ago
2000
IEEE
Even though high-level hardware synthesis from dataflow graphs becomes popular in designing DSP systems, currently used dataflow models are inefficient to deal with emerging multi...