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ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
14 years 3 months ago
Two efficient methods to reduce power and testing time
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
Il-soo Lee, Tony Ambler
ICCD
1999
IEEE
93views Hardware» more  ICCD 1999»
14 years 2 months ago
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
If a system-on-a-chip (SOC) contains an embedded processor, this paper presents a novel approach for using the processor to aid in testing the other components of the SOC. The bas...
Abhijit Jas, Nur A. Touba
HOTSWUP
2009
ACM
14 years 2 months ago
Efficient Systematic Testing for Dynamically Updatable Software
Recent years have seen significant advances in dynamic software updating (DSU) systems, which allow programs to be patched on the fly. However, a significant challenge remains: Ho...
Christopher M. Hayden, Eric A. Hardisty, Michael W...
VTS
2006
IEEE
102views Hardware» more  VTS 2006»
14 years 4 months ago
Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes
We consider self-testing of complete wireless nodes in the field through a low-energy software-based selftest (SBST) method. Energy consumption is optimized both for individual co...
Rong Zhang, Zeljko Zilic, Katarzyna Radecka
VTS
2002
IEEE
108views Hardware» more  VTS 2002»
14 years 3 months ago
On Using Efficient Test Sequences for BIST
High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Inp...
René David, Patrick Girard, Christian Landr...