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ESTIMEDIA
2008
Springer
13 years 8 months ago
Serialized multitasking code generation from dataflow specification
This paper is concerned about multitasking embedded software development from the system specification to the final implementation including design space exploration(DSE). In the ...
Seongnam Kwon, Soonhoi Ha
ICSE
2008
IEEE-ACM
14 years 6 months ago
CCVisu: automatic visual software decomposition
Understanding the structure of large existing (and evolving) software systems is a major challenge for software engineers. In reverse engineering, we aim to compute, for a given s...
Dirk Beyer
CODES
2005
IEEE
14 years 9 days ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
DAC
1997
ACM
13 years 11 months ago
More Practical Bounded-Skew Clock Routing
: Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot ...
Andrew B. Kahng, Chung-Wen Albert Tsao
DAC
2009
ACM
14 years 7 months ago
Multicore parallel min-cost flow algorithm for CAD applications
Computational complexity has been the primary challenge of many VLSI CAD applications. The emerging multicore and manycore microprocessors have the potential to offer scalable perf...
Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng