116 search results - page 23 / 24 » Electromigration-Aware Physical Design of Integrated Circuit... |
GLVLSI
2010
IEEE
14 years 2 months ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
ISCA
2007
IEEE
14 years 4 months ago
2007
IEEE
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
DAC
2008
ACM
14 years 10 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
ISPD
2005
ACM
14 years 3 months ago
2005
ACM
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
ICCAD
2003
IEEE
2003
IEEE
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
14 years 6 months ago
In this paper we present a family of multi-objective hypergraph partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both th...