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DATE
2006
IEEE
114views Hardware» more  DATE 2006»
14 years 3 months ago
An efficient static algorithm for computing the soft error rates of combinational circuits
Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorit...
Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Denni...
GLVLSI
2006
IEEE
115views VLSI» more  GLVLSI 2006»
14 years 3 months ago
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
Song Peng, Rajit Manohar
ICCAD
1994
IEEE
115views Hardware» more  ICCAD 1994»
14 years 2 months ago
Fast transient power and noise estimation for VLSI circuits
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
Wolfgang T. Eisenmann, Helmut E. Graeb
DAC
2003
ACM
14 years 3 months ago
Realizable RLCK circuit crunching
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Isma...
WWW
2009
ACM
14 years 10 months ago
Seller's credibility in electronic markets: a complex network based approach
In the last decade, there has been an explosion of online commercial activity enabled by the World Wide Web. An electronic marketplace (e-market) provides an online method to perf...
Adriano M. Pereira, Arlei Silva, Wagner Meira Jr.,...