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DATE
1999
IEEE
74views Hardware» more  DATE 1999»
13 years 12 months ago
FSMD Functional Partitioning for Low Power
Previous work has shown that sizable power reductions can be achieved by shutting down a system's sub-circuits when they are not needed. However, these shutdown techniques fo...
Enoch Hwang, Frank Vahid, Yu-Chin Hsu
ISSS
2002
IEEE
154views Hardware» more  ISSS 2002»
14 years 14 days ago
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edw...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 7 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
DSN
2009
IEEE
13 years 11 months ago
Processor reliability enhancement through compiler-directed register file peak temperature reduction
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliab...
Chengmo Yang, Alex Orailoglu
PAA
2008
13 years 7 months ago
Prototype reduction using an artificial immune model
Artificial immune system (AIS)-based pattern classification approach is relatively new in the field of pattern recognition. The study explores the potentiality of this paradigm in ...
Utpal Garain