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DAC
1994
ACM
13 years 11 months ago
Clock Grouping: A Low Cost DFT Methodology for Delay Testing
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
Wen-Chang Fang, Sandeep K. Gupta
EWCBR
2006
Springer
13 years 11 months ago
Complexity Profiling for Informed Case-Base Editing
Abstract. The contents of the case knowledge container is critical to the performance of case-based classification systems. However the knowledge engineer is given little support i...
Stewart Massie, Susan Craw, Nirmalie Wiratunga
ISPASS
2007
IEEE
14 years 1 months ago
Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads
Address re-mapping techniques in so-called active memory systems have been shown to dramatically increase the performance of applications with poor cache and/or communication beha...
Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark Heinric...
DAC
2003
ACM
14 years 8 months ago
On-chip logic minimization
While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such a...
Roman L. Lysecky, Frank Vahid
HYBRID
2009
Springer
13 years 10 months ago
Three-Dimensional Kneed Bipedal Walking: A Hybrid Geometric Approach
A 3D biped with knees and a hip is naturally modeled as a nontrivial hybrid system; impacts occur when the knee strikes and when the foot impacts the ground causing a switch in the...
Aaron D. Ames, Ryan W. Sinnet, Eric D. B. Wendel