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VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
14 years 3 months ago
Implementing the Best Processor Cores
It is well-known that varying architectural, technological and implementation aspects of embedded microprocessors, such as ARM, can produce widely differing performance and power ...
Vamsi Boppana, Rahoul Varma, S. Balajee
RTAS
2005
IEEE
14 years 2 months ago
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
Sibin Mohan, Frank Mueller, David B. Whalley, Chri...
DATE
1998
IEEE
153views Hardware» more  DATE 1998»
14 years 1 months ago
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
Jan M. Rabaey, Marlene Wan
DATE
2008
IEEE
102views Hardware» more  DATE 2008»
14 years 3 months ago
Vectorization of Reed Solomon Decoding and Mapping on the EVP
Reed Solomon (RS) codes are used in a variety of (wireless) communication systems. Although commonly implemented in dedicated hardware, this paper explores the mapping of high-thr...
Akash Kumar, Kees van Berkel
ECRTS
2008
IEEE
14 years 3 months ago
Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson