Sciweavers

1742 search results - page 268 / 349
» Embedded MPLS Architecture
Sort
View
LCTRTS
2004
Springer
14 years 2 months ago
Link-time optimization of ARM binaries
The overhead in terms of code size, power consumption and execution time caused by the use of precompiled libraries and separate compilation is often unacceptable in the embedded ...
Bruno De Bus, Bjorn De Sutter, Ludo Van Put, Domin...
SAMOS
2004
Springer
14 years 2 months ago
High-Speed Event-Driven RTL Compiled Simulation
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
Alexey Kupriyanov, Frank Hannig, Jürgen Teich
SCOPES
2004
Springer
14 years 2 months ago
An Integer Linear Programming Approach to Classify the Communication in Process Networks
New embedded signal processing architectures are emerging that are composed of loosely coupled heterogeneous components like CPUs or DSPs, specialized IP cores, reconfigurable uni...
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
14 years 2 months ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...
CODES
2003
IEEE
14 years 2 months ago
Deriving process networks from weakly dynamic applications in system-level design
We present an approach to the automatic derivation of executable Process Network specifications from Weakly Dynamic Applications. We introduce the notions of Dynamic Single Assig...
Todor Stefanov, Ed F. Deprettere