Sciweavers

1742 search results - page 301 / 349
» Embedded MPLS Architecture
Sort
View
CODES
2005
IEEE
14 years 1 months ago
A power estimation methodology for systemC transaction level models
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan
CODES
2005
IEEE
14 years 1 months ago
Dynamic phase analysis for cycle-close trace generation
For embedded system development, several companies provide cross-platform development tools to aid in debugging, prototyping and optimization of programs. These are full system em...
Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh...
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
14 years 1 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
DATE
2005
IEEE
135views Hardware» more  DATE 2005»
14 years 1 months ago
Compositional Memory Systems for Multimedia Communicating Tasks
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
ECRTS
2005
IEEE
14 years 1 months ago
A WCET-Oriented Static Branch Prediction Scheme for Real Time Systems
Branch prediction mechanisms are becoming commonplace within current generation processors. Dynamic branch predictors, albeit able to predict branches quite accurately in average,...
François Bodin, Isabelle Puaut