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DATE
2005
IEEE
151views Hardware» more  DATE 2005»
14 years 1 months ago
Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications
Instruction Level Parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and...
Domenico Barretta, William Fornaciari, Mariagiovan...
LCPC
2000
Springer
13 years 11 months ago
Improving Offset Assignment for Embedded Processors
Embedded systems consisting of the application program ROM, RAM, the embedded processor core, and any custom hardware on a single wafer are becoming increasingly common in applicat...
Sunil Atri, J. Ramanujam, Mahmut T. Kandemir
DAC
1999
ACM
14 years 8 months ago
Customized Instruction-Sets for Embedded Processors
It is generally believed that there will be little more variety in CPU architectures, and thus the design of Instruction-set Architectures (ISAs) will have no role in the future o...
Joseph A. Fisher
PATMOS
2005
Springer
14 years 27 days ago
Area-Aware Pipeline Gating for Embedded Processors
Modern embedded processors use small and simple branch predictors to improve performance. Using complex and accurate branch predictors, while desirable, is not possible as such pre...
Babak Salamat, Amirali Baniasadi
DFT
2002
IEEE
128views VLSI» more  DFT 2002»
14 years 11 days ago
Matrix-Based Test Vector Decompression Using an Embedded Processor
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
Kedarnath J. Balakrishnan, Nur A. Touba