Sciweavers

550 search results - page 108 / 110
» Embedded System Architecture Design Based on Real-Time Emula...
Sort
View
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
14 years 29 days ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
LCTRTS
2010
Springer
14 years 2 months ago
Operation and data mapping for CGRAs with multi-bank memory
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunh...
CASES
2009
ACM
14 years 1 months ago
Fine-grain performance scaling of soft vector processors
Embedded systems are often implemented on FPGA devices and 25% of the time [2] include a soft processor— a processor built using the FPGA reprogrammable fabric. Because of their...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
14 years 18 days ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
EMSOFT
2005
Springer
14 years 26 days ago
Model-based run-time monitoring of end-to-end deadlines
The correct interplay among components in a distributed, reactive system is a crucial development task, particularly for embedded systems such as those in the automotive domain. M...
Jaswinder Ahluwalia, Ingolf H. Krüger, Walter...