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ISLPED
2010
ACM
204views Hardware» more  ISLPED 2010»
13 years 10 months ago
Variation aware performance analysis of gain cell embedded DRAMs
Gain cell embedded DRAMs are twice as dense as 6T SRAMs, are logic compatible, have decoupled read and write paths providing good low voltage margin, and can drive long bitlines w...
Wei Zhang, Ki Chul Chun, Chris H. Kim
ISCAS
2007
IEEE
167views Hardware» more  ISCAS 2007»
14 years 4 months ago
An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM
— Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells in standby mode reduces the leakage curren...
Afshin Nourivand, Chunyan Wang, M. Omair Ahmad
ISLPED
1996
ACM
103views Hardware» more  ISLPED 1996»
14 years 1 months ago
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving
This paper proposes a 0.5V / 100MHz / sub-5mW-operated 1-Mbit SRAM cell architecture which uses an overVCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimi...
Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, ...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 6 months ago
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
Xiaoyao Liang, Kerem Turgay, David Brooks
VTS
2005
IEEE
95views Hardware» more  VTS 2005»
14 years 3 months ago
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
Baosheng Wang, Yuejian Wu, Josh Yang, André...