395 search results - page 26 / 79 » Encoding Algorithms for Logic Synthesis |
124
Voted
CEC
2003
IEEE
15 years 6 months ago
2003
IEEE
Evolutionary computation presents a new paradigm shift in hardware design and synthesis. According to this paradigm, hardware design is pursued by deriving inspiration from biologi...
125
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ICCAD
1997
IEEE
15 years 6 months ago
1997
IEEE
In this paper we present an algorithm for converting a BDD representation of a logic function into a multiple-level netlist of disjoint-support subfunctions. On the theoretical si...
ARITH
1999
IEEE
15 years 6 months ago
1999
IEEE
A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm i...
133
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DAC
2003
ACM
16 years 3 months ago
2003
ACM
A binary decoder is a common component of software development tools such as instruction set simulators, disassemblers and debuggers. The efficiency of the decoder can have a sign...
110
Voted
ASPDAC
2007
ACM
15 years 6 months ago
2007
ACM
In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used Assertion...