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ICCD
2004
IEEE
96views Hardware» more  ICCD 2004»
14 years 4 months ago
Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study
Dynamic address compression schemes that exploit address locality can help reduce both address bus energy and cost simultaneously with only a small performance penalty. In this wo...
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Maha...
DATE
2006
IEEE
132views Hardware» more  DATE 2006»
14 years 1 months ago
Energy reduction by workload adaptation in a multi-process environment
Reducing energy consumption is an important issue in modern computers. Dynamic power management (DPM) has been extensively studied in recent years. One approach for DPM is to adju...
Changjiu Xian, Yung-Hsiang Lu
IPPS
2008
IEEE
14 years 1 months ago
DC-SIMD : Dynamic communication for SIMD processors
SIMD (single instruction multiple data)-type processors have been found very efficient in image processing applications, because their repetitive structure is able to exploit the...
Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Co...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 13 days ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
FCCM
2002
IEEE
119views VLSI» more  FCCM 2002»
14 years 9 days ago
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy
We examine the energy savings possible by re-mapping critical software loops from a microprocessor to configurable logic appearing on the same-chip in commodity chips now commerci...
Greg Stitt, Brian Grattan, Jason R. Villarreal, Fr...