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» Energy exploration and reduction of SDRAM memory systems
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GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
14 years 8 days ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
ISCA
2010
IEEE
305views Hardware» more  ISCA 2010»
14 years 16 days ago
Rethinking DRAM design and organization for energy-constrained multi-cores
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...
SCOPES
2007
Springer
14 years 1 months ago
Operating system integrated energy aware scratchpad allocation strategies for multiprocess applications
Various scratchpad allocation strategies have been developed in the past. Most of them target the reduction of energy consumption. These approaches share the necessity of having d...
Robert Pyka, Christoph Faßbach, Manish Verma...
CODES
2005
IEEE
14 years 1 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
ISLPED
2006
ACM
109views Hardware» more  ISLPED 2006»
14 years 1 months ago
Power reduction of multiple disks using dynamic cache resizing and speed control
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
Le Cai, Yung-Hsiang Lu