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» Energy minimization using multiple supply voltages
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PLDI
2003
ACM
14 years 26 days ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
Fen Xie, Margaret Martonosi, Sharad Malik
ICCAD
2001
IEEE
127views Hardware» more  ICCAD 2001»
14 years 4 months ago
What is the Limit of Energy Saving by Dynamic Voltage Scaling?
Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency based on the computation load to provide desired performance with the minimal amoun...
Gang Qu
DATE
2005
IEEE
120views Hardware» more  DATE 2005»
14 years 1 months ago
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Supply voltage scaling and adaptive body-biasing are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting...
Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Z...
TVLSI
2002
107views more  TVLSI 2002»
13 years 7 months ago
Low-power clock distribution using multiple voltages and reduced swings
: Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low...
Jatuchai Pangjun, Sachin S. Sapatnekar
VLSID
2003
IEEE
134views VLSI» more  VLSID 2003»
14 years 8 months ago
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
Saraju P. Mohanty, N. Ranganathan