114 search results - page 9 / 23 » Energy-efficient FPGA interconnect design |
118
Voted
GLVLSI
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template ar...
123
Voted
TVLSI
2010
14 years 10 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
143
Voted
FPT
2005
IEEE
15 years 9 months ago
2005
IEEE
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
127
Voted
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
—Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencie...
112
Voted
ICCAD
2001
IEEE
16 years 16 days ago
2001
IEEE
In this paper, we utilize Rent’s rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design c...