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» Enhanced leakage reduction Technique by gate replacement
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DAC
1999
ACM
13 years 11 months ago
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...
Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye,...
SOCC
2008
IEEE
106views Education» more  SOCC 2008»
14 years 1 months ago
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control
First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With s...
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
TVLSI
2010
13 years 2 months ago
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particula...
Mohammad Taherzadeh-Sani, Anas A. Hamoui
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
14 years 1 months ago
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits
—Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional k...
Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen
ASPDAC
2009
ACM
164views Hardware» more  ASPDAC 2009»
13 years 11 months ago
High-performance global routing with fast overflow reduction
Global routing is an important step for physical design. In this paper, we develop a new global router, NTUgr, that contains three major steps: prerouting, initial routing, and enh...
Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang