56 search results - page 8 / 12 » Enhancing test efficiency for delay fault testing using mult... |
ARVLSI
1999
IEEE
14 years 1 days ago
1999
IEEE
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
VTS
2008
IEEE
14 years 2 months ago
2008
IEEE
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, ...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
The presence of unknown values in the simulation result is a key barrier to effective output response compaction in practice. This paper proposes a simple circuit module, called a...
DFT
2003
IEEE
14 years 1 months ago
2003
IEEE
A new hybrid BIST scheme is proposed which is based on using an “incrementally guided LFSR.” It very efficiently combines external deterministic data from the tester with on-c...
PAMI
2008
13 years 7 months ago
2008
In this work, we propose the use of a modified version of the correlation coefficient as a performance criterion for the image alignment problem. The proposed modification has the ...