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ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
13 years 11 months ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...
ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
14 years 4 months ago
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Abstract— Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a us...
Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan ...
VTS
2007
IEEE
203views Hardware» more  VTS 2007»
14 years 2 months ago
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...
Avijit Dutta, Nur A. Touba
ICASSP
2011
IEEE
12 years 11 months ago
Application control for fast adaptive error resilient H.264/AVC streaming over IP wireless networks
Following the joint source and channel coding paradigm, we propose in this article an application controlling strategy to allow fast adaptation of multimedia transmission to the i...
Catherine Lamy-Bergot, Benjamin Gadat
TVLSI
1998
118views more  TVLSI 1998»
13 years 7 months ago
Automatic generation of error control codes for computer applications
— This paper proposes a methodology, implemented in a tool, to automatically generate the main classes of error control codes (ECC’s) widely applied in computer memory systems ...
Franco Fummi, Donatella Sciuto, Cristina Silvano