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ICSE
2001
IEEE-ACM
13 years 12 months ago
Dynamic and Selective Combination of Extensions in Component-Based Applications
Support for dynamic and client-specific customization is required in many application areas. We present a (distributed) application as consisting of a minimal functional core – ...
Eddy Truyen, Bart Vanhaute, Wouter Joosen, Pierre ...
ASPDAC
1998
ACM
81views Hardware» more  ASPDAC 1998»
13 years 11 months ago
A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks
—An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products exp...
Debatosh Debnath, Tsutomu Sasao
FPGA
1998
ACM
146views FPGA» more  FPGA 1998»
13 years 11 months ago
Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation
In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a K-input LUT, but a...
Jason Cong, Yean-Yow Hwang
DAC
1996
ACM
13 years 11 months ago
Test Point Insertion: Scan Paths through Combinational Logic
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses th...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
13 years 11 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang