96 search results - page 8 / 20 » Espresso-Signature: A New Exact Minimizer for Logic Function... |
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
Synthesis of reversible logic has become a very important research area. In recent years several algorithms ? heuristic as well as exact ones ? have been introduced in this area. ...
IJCV
2011
13 years 2 months ago
2011
This paper is devoted to the optimization problem of continuous multipartitioning, or multi-labeling, which is based on a convex relaxation of the continuous Potts model. In contr...
ASPDAC
2004
ACM
14 years 27 days ago
2004
ACM
— In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial an...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) -- representation...