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» Estimating design time for system circuits
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FCCM
1998
IEEE
148views VLSI» more  FCCM 1998»
13 years 11 months ago
JHDL - An HDL for Reconfigurable Systems
JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard pro...
Peter Bellows, Brad L. Hutchings
GLVLSI
2003
IEEE
219views VLSI» more  GLVLSI 2003»
14 years 20 days ago
Buffer sizing for minimum energy-delay product by using an approximating polynomial
This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next the paper descri...
Chang Woo Kang, Soroush Abbaspour, Massoud Pedram
JUCS
2007
114views more  JUCS 2007»
13 years 7 months ago
Design and Implementation of the AMCC Self-Timed Microprocessor in FPGAs
: The development of processors with full custom technology has some disadvantages, such as the time used to design the processors and the cost of the implementation. In this artic...
Susana Ortega-Cisneros, Juan Jóse Raygoza-P...
DAC
2006
ACM
14 years 8 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
VTC
2006
IEEE
117views Communications» more  VTC 2006»
14 years 1 months ago
Design and Implementation of Robust Time/Frequency Offset Tracking Algorithm for MIMO-OFDM Receivers
— In this paper, the robust time and frequency offset tracking algorithms and architecture for high throughput wireless local area network (WLAN) systems are presented. The desig...
Il-Gu Lee, Heejung Yu, Eunyoung Choi, Jungbo Son, ...