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» Estimating design time for system circuits
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TCOM
2010
80views more  TCOM 2010»
13 years 5 months ago
Near optimal training sequences for low complexity symbol timing estimation in MIMO systems
—Training sequences for data-aided timing estimation in multi-input multi-output systems are designed. It is observed that for low complexity implementation, the sequences must n...
Ketan Rajawat, Ajit K. Chaturvedi
DAC
2007
ACM
14 years 8 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 9 days ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
ICCAD
1996
IEEE
151views Hardware» more  ICCAD 1996»
13 years 11 months ago
Expected current distributions for CMOS circuits
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
Dennis J. Ciplickas, Ronald A. Rohrer
FPL
2007
Springer
128views Hardware» more  FPL 2007»
14 years 1 months ago
Embedded Programmable Logic Core Enhancements for System Bus Interfaces
Programmable logic cores (PLCs) offer a means of providing post-fabrication re-configurability to a SoC design. Circuits implemented in a PLC will inevitably have lower timing per...
Bradley R. Quinton, Steven J. E. Wilton