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ICCAD
2000
IEEE
100views Hardware» more  ICCAD 2000»
14 years 2 days ago
Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering
For data dominated applications, the system level design trajectory should first focus on finding a good data transfer and storage solution. Since no realization details are avail...
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. ...
DAC
2006
ACM
14 years 8 months ago
Rapid estimation of control delay from high-level specifications
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
14 years 27 days ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
ASPDAC
2005
ACM
98views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Bitwidth-aware scheduling and binding in high-level synthesis
- Many high-level description languages, such as C/C++ or Java, lack the capability to specify the bitwidth information for variables and operations. Synthesis from these specifica...
Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, J...
RSP
2006
IEEE
102views Control Systems» more  RSP 2006»
14 years 1 months ago
Rapid Resource-Constrained Hardware Performance Estimation
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driv...
Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrish...