501 search results - page 39 / 101 » Evaluating CMPs and Their Memory Architecture |
CODES
1999
IEEE
14 years 10 hour ago
1999
IEEE
The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching...
DATE
1999
IEEE
14 years 8 hour ago
1999
IEEE
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
ISCA
1993
IEEE
13 years 11 months ago
1993
IEEE
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
ITC
2003
IEEE
14 years 29 days ago
2003
IEEE
1 This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a progr...
JUCS
2000
13 years 7 months ago
2000
: Since the era of vector and pipelined computing, the computational speed is limited by the memory access time. Faster caches and more cache levels are used to bridge the growing ...