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» Evaluating Fault Emulation on FPGA
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DATE
2010
IEEE
145views Hardware» more  DATE 2010»
14 years 17 days ago
An evaluation of a slice fault aware tool chain
Abstract—As FPGA sizes and densities grow, their manufacturing yields decrease. This work looks toward reclaiming some of this lost yield. Several previous works have suggested f...
Adwait Gupte, Phillip Jones
DFT
2003
IEEE
99views VLSI» more  DFT 2003»
14 years 23 days ago
Dependability Analysis of CAN Networks: An Emulation-Based Approach
1 Today many safety-critical applications are based on distributed systems where several computing nodes exchange information via suitable network interconnections. An example of t...
J. Pérez, Matteo Sonza Reorda, Massimo Viol...
VLSI
2007
Springer
14 years 1 months ago
Impact of hardware emulation on the verification quality improvement
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
Youssef Serrestou, Vincent Beroulle, Chantal Robac...
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
14 years 1 months ago
A Complete Network-On-Chip Emulation Framework
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
ICES
2005
Springer
176views Hardware» more  ICES 2005»
14 years 1 months ago
Consensus-Based Evaluation for Fault Isolation and On-line Evolutionary Regeneration
While the fault repair capability of Evolvable Hardware (EH) approaches have been previously demonstrated, further improvements to fault handling capability can be achieved by exp...
Kening Zhang, Ronald F. DeMara, Carthik A. Sharma