1304 search results - page 130 / 261 » Evaluating Hardware Compilation Techniques |
162
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DAC
2006
ACM
16 years 5 months ago
2006
ACM
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
129
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ACSC
2008
IEEE
15 years 11 months ago
2008
IEEE
In the future, if we are to continue to expect improved application performance we will have to achieve it by exploiting course-grained hardware parallelism rather then simply rel...
149
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ISCA
2007
IEEE
15 years 11 months ago
2007
IEEE
The recently released SPEC CPU2006 benchmark suite is expected to be used by computer designers and computer architecture researchers for pre-silicon early design analysis. Partia...
160
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MICRO
2006
IEEE
15 years 10 months ago
2006
IEEE
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...
137
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DATE
2003
IEEE
15 years 10 months ago
2003
IEEE
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...