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» Evaluating Hardware Compilation Techniques
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ICDE
2010
IEEE
202views Database» more  ICDE 2010»
14 years 7 months ago
Generating code for holistic query evaluation
We present the application of customized code generation to database query evaluation. The idea is to use a collection of highly efficient code templates and dynamically instantiat...
Konstantinos Krikellas, Marcelo Cintra, Stratis Vi...
ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
14 years 4 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
DATE
2005
IEEE
84views Hardware» more  DATE 2005»
14 years 1 months ago
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms
In this paper, we present a software compilation approach for microprocessor/FPGA platforms that partitions a software binary onto custom hardware implemented in the FPGA. Our app...
Greg Stitt, Frank Vahid
MICRO
1996
IEEE
142views Hardware» more  MICRO 1996»
13 years 12 months ago
Compiler Synthesized Dynamic Branch Prediction
Branch prediction is the predominant approach for minimizing the pipeline breaks caused by branch instructions. Traditionally, branch prediction is accomplished in one of two ways...
Scott A. Mahlke, Balas K. Natarajan
IFIPPACT
1994
13 years 9 months ago
Microcode Generation for Flexible Parallel Target Architectures
: Advanced architectural features of microprocessors like instruction level parallelism and pipelined functional hardware units require code generation techniques beyond the scope ...
Rainer Leupers, Wolfgang Schenk, Peter Marwedel