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» Evaluating Hardware Compilation Techniques
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DATE
2004
IEEE
139views Hardware» more  DATE 2004»
13 years 11 months ago
Flexible Software Protection Using Hardware/Software Codesign Techniques
A strong level of trust in the software running on an embedded processor is a prerequisite for its widespread deployment in any high-risk system. The expanding field of software p...
Joseph Zambreno, Alok N. Choudhary, Rahul Simha, B...
EUROPAR
2000
Springer
13 years 11 months ago
Design and Evaluation of a Compiler-Directed Collective I/O Technique
Abstract. Current approaches to parallel I/O demand extensive user effort to obtain acceptable performance. This is in part due to difficulties in understanding the characteristics...
Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhar...
TCAD
2008
127views more  TCAD 2008»
13 years 7 months ago
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozor...
DATE
1998
IEEE
165views Hardware» more  DATE 1998»
13 years 12 months ago
AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems
Attribute grammars have been used extensively in every phase of traditional compiler construction. Recently, it has been shown that they can also be effectively adopted to handle ...
George Economakos, George K. Papakonstantinou, Pan...
ISSS
1995
IEEE
104views Hardware» more  ISSS 1995»
13 years 11 months ago
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis
One of the key issues in hardware/software{cosynthesis is precise estimation. The usual local estimation techniques are inadequate for globally optimising compilers and synthesis ...
Jörg Henkel, Rolf Ernst